1. Field of the Invention
The present invention relates to a high performance intermediate stage for an operational amplifier (opamp), where the opamp accepts a rail-to-rail input voltage and provides a rail-to-rail output voltage. More particularly, the present invention relates to an intermediate stage with a floating current source used to bias two current mirrors, where the floating current source has circuitry configured to minimize input offset voltage and to provide currents which do not vary with changes in the voltage rails or the common-mode input voltage.
2. Background
FIG. 1 shows typical circuitry for an opamp which accepts a rail-to-rail input voltage, or voltage ranging between the VDD and VSS voltage supply rails, and provides a rail-to-rail output voltage. The circuit includes an input stage 100, an intermediate stage 150, and an output stage 190.
The input stage 100 is formed by transistors 101-104, a current source 106 and a current source 108. The gates of transistors 101 and 102 provide the inverting input VINxe2x88x92 for the opamp, while the gates of transistors 103 and 104 provide the noninverting input VIN+. The current source 106 drives the sources of transistors 101 and 104, while the drains of transistors 101 and 104 provide current signals IIP+ and IIPxe2x88x92 to the intermediate stage 150. The current source 108 provides current to the sources of transistors 102 and 103, while the drains of transistors 102 and 103 provide current signals IINxe2x88x92 and IIN+ to the intermediate stage. Transistors 101 and 104 are PMOS transistors as illustrated by the circle provided on their gate, while transistors 102 and 103 are NMOS devices without such a gate circle. The gate circles are used to show which transistors are PMOS and NMOS devices in the remaining transistors of FIG. 1, as well as in transistors in subsequent figures.
The intermediate stage 150 includes two current mirrors, a first current mirror with transistors 151-154, and a second current mirror with transistors 155-158. The intermediate stage also includes voltage supplies 160 and 162. The voltage supply 160 biases the gates of transistors 153 and 154, while the voltage supply 162 biases the gates of transistors 155 and 156.
The intermediate stage further includes a current source 164 set to provide a current to bias the gates of current mirror transistors 151 and 152 and to drive the drain of transistor 153. A current source 166 biases the gates of current mirror transistors 157 and 158 and provides current from the drain of transistor 155.
Outputs IOP and ION of the intermediate stage are provided from the source and drain of transistors 170 and 180 with source-drain paths connected in parallel between the drains of transistors 154 and 156. Transistors 171 and 172 are diode connected transistors which set the bias voltage on the gate of transistor 170. A current source 173 drives the gate of transistor 170 as well as transistors 171 and 172. Transistors 181 and 182 are diode connected transistors which set the bias voltage on the gate of transistor 180. A current source 183 provides current to transistors 181 and 182 to bias the gate of transistor 180.
The output stage 190 includes output driver transistors 192 and 194 connected between the rails VDD and VSS. The common drains of transistors 192 and 194 provide the output of the CMOS opamp of FIG. 1. The gate of transistor 192 is driven by the output IOP of the intermediate stage. The gate of transistor 194 is driven by the output ION of the intermediate stage. A capacitor 196 is connected between the gate of transistor 192 and its drain to provide Miller Effect frequency compensation. Similarly, a capacitor 198 is provided between the gate and drain of transistor 194.
The intermediate stage provides a stable class A-B control for the output stage independent of common-mode input and supply rail voltages. A drawback to the circuit is that any mismatch between the current sources 164 and 166 will reflect forward as an input offset. The circuit of FIG. 1 is described in Hogervorst, et al., xe2x80x9cA Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier For VLSI Cell Librariesxe2x80x9d, IEEE Journal Of Solid-State Circuits, Vol. 29, No. 12, December 1994, which is incorporated herein by reference (xe2x80x98the Hogervorst referencexe2x80x99).
FIG. 2 shows modifications to the intermediate stage circuit 150 of FIG. 1 to overcome the problem of input offset being reflected forward due to a mismatch between current sources 164 and 166. The intermediate stage circuit of FIG. 2 includes an ideal floating current source 200 which is used instead of current sources 164 and 166. The ideal floating current source 200 connects the gates of current mirror transistors 157-158 and drain of transistor 155 to the gates of current mirror transistors 151-152 and drain of transistor 153. The constant values of the floating current source 200 together with the current sources 171 and 173 control the output stage""s quiescent current to be constant. Note that components carried over from FIG. 1 to FIG. 2 are similarly labeled, as are components carried over in subsequent figures.
FIG. 3 shows one implementation of circuitry to provide the ideal floating current source 200 of FIG. 2. The ideal floating current source includes two transistors 304 and 312 with source to drain paths connected in parallel between the drains of transistors 153 and 155. The gate of transistor 304 has a voltage set by diode connected transistors 300 and 302 and is driven by current source 306 to the VDD voltage rail. The gate of transistor 312 has a voltage set by diode connected transistors 308 and 310 and is connected by a current source 314 to the VSS voltage rail. As configured, the transistors 304 and 312 provide two identical current sources between current mirrors formed by transistors 151-154 and transistors 155-158, so that the current source transistors 304 and 312 do not reflect forward an input offset voltage, unlike the current sources 164 and 166 of FIG. 1 which may be mismatched.
The bias currents of transistors 304 and 312 will change when the common mode input cuts off one of the currents IINxe2x88x92/IIN+ and IIP+/IIPxe2x88x92. If the input common mode value goes to VSS, then IIN+/IINxe2x88x92 will collapse to zero current. If that happens, the current mirror 155-158 will change DC operating voltage, and the PMOS transistor 312 will change its gate to source voltage, and therefore assume a new bias current to change the A-B point for the output stage. Similarly, if the input common mode value goes to VDD, IIP+/IIPxe2x88x92 will collapse to zero current, the current mirror 151-154 will change operating voltage, and the NMOS transistor 304 will change its gate-to-source voltage. The NMOS transistor 304 will, therefore, assume a new bias current to change the A-B point for the output stage. The transistors 312 and 304 are, thus, sensitive to input common mode changes. The current of the floating current source will, thus, change with the common-mode input voltage, and therefore the quiescent current of the output stage will also change to compensate for the common mode input voltage. The circuitry of FIG. 3 is described in the Hogervorst reference cited previously.
FIG. 4 shows another circuit implementation for the ideal floating current source 200 of FIG. 2. The current source includes two transistors 402 and 404 with source to drain paths connected in series between the drains of transistors 153 and 155. The gate of transistor 402 is driven by a current source 405 and is further connected to one leg of a current mirror formed by transistors 406 and 407. The other leg of the current mirror formed by transistors 406 and 407 is connected to the gate of transistor 404. An additional diode connected transistor 410 connects the VDD power supply rail to the gate of transistor 404. As configured, the transistors 402 and 404 provide two identical current sources between current mirrors formed by transistors 151-154 and transistors 155-158, so that the current source transistors 402 and 404 do not reflect forward an input offset voltage, unlike the current sources 164 and 166 of FIG. 1 which may be mismatched. The circuit of FIG. 4 is described in Moldovan, et al., xe2x80x9cA Rail-to-Rail Constant Gain, Buffered Op-Amp For Real Time Video Applicationsxe2x80x9d, IEEE Journal Of Solid-State Circuits, Vol. 32, No. 2, February 1997, which is incorporated herein by reference.
In FIG. 4, the value of the floating current source formed by transistors 402 and 404 is determined by the difference between the gate voltages of transistors 402 and 404. The gate to source voltage of transistor 410 relative to VDD, and the gate to source voltage of transistor 406 relative to VSS serve to set the value of the gate voltage difference. Therefore, the value of the floating current source, and the output stage""s quiescent current will also change significantly with changes in the supply voltage rails VDD and VSS. The virtue of the circuit of FIG. 4 is that transistors 402 and 404 are in the saturation region, so a common-mode input change does not change the circuit quiescent operating point.
It is desirable to provide an intermediate stage for a rail-to-rail input/output CMOS opamp which does not have an output stage""s quiescent current which varies with changes in the common-mode input voltage or the voltage rails, while still providing circuitry to minimize any input voltage offset.
In accordance with the present invention, circuitry is provided for an intermediate stage for a rail-to-rail input/output CMOS opamp which has an output quiescent current which does not vary with changes in the voltage rails and common-mode input voltage, and which eliminates input offset caused by the mismatch of the two current sources (164,166) in the circuit of FIG. 1.
In accordance with the present invention, an intermediate stage is provided which includes a floating current source. Referring to FIG. 5, the floating current source includes a floating current mirror made up of NMOS transistors 500, 501 and 502 and PMOS transistors 503, 504 and 505. The NMOS transistor 502 has a source-drain path provided in series with a PMOS transistor 505 serving to connect the current mirrors 151-154 and 155-158. As with the circuit of FIG. 3, the transistors 502 and 505 are biased to provide identical current sources serving to prevent input offset from being reflected forward, unlike with the two current sources 164 and 166 of FIG. 1 which may be mismatched. The transistors 502 and 505 are further biased to eliminate the problem occurring when the common mode input cuts off one of the currents IINxe2x88x92/IIN+ and IIP+/IIPxe2x88x92, in a manner similar to the circuitry of FIG. 4.
The ideal current source in accordance with the present invention further includes a current source 508 providing current from the VDD voltage rail to the drain and gate of NMOS transistor 500. Unlike circuitry in FIG. 3, the source of transistor 500 is separated from the VSS rail by a PMOS transistor 503 enabling the current mirror transistors 500, 501, 502, 503, 504 and 505 to form a floating current mirror with a gate bias voltage independent of changes in the voltage on the voltage supply rails VDD and VSS.
In further embodiments in accordance with the present invention, a floating current source can be created using transistors 500 and 503 in combination with transistors 501 and 504, similar to that shown in FIG. 5. As illustrated in FIGS. 6, the drain of PMOS transistor 503 can be connected to the VSS supply or some other bias point near it in voltage, as long as PMOS transistor 503 is maintained in saturation. In the same way, the drain of the NMOS transistor 500 can be connected to the VDD supply or some other bias point near it in voltage, as shown in FIG. 7. Further, either of transistors 500 or 503 can be connected in a diode configuration, although transistor 503 is shown in the diode configuration in FIG. 5.
The transistors 501, 504, 506 and 507 can be included to provide a stable voltage reference to replace voltage supplies 160 and 162 of FIG. 1. The transistors 501 and 504 are separated from the power supply rails VDD and VSS by diode connected transistors 506 and 507. The gate of transistor 506 provides a stable bias voltage to the gates of current mirror transistors 155 and 156, eliminating the need for the voltage supply 162 of FIG. 1. The gate of transistor 507 provides a stable bias voltage to the gates of transistors 153 and 154, eliminating the need for the voltage supply 160 of FIG. 1.
Referring to FIG. 8, an intermediate stage for an opamp in accordance with the present invention can include clamping transistors 800 and 802 to enable low voltage transistors to be used. The transistors 800 and 802 serve to clamp the drain-source voltage across transistors 154 and 156 to be less than the total gate-source voltages of transistors 181 and 800 and that of transistors 172 and 802, respectively. Without such clamping, the voltage across transistors 154 and 156 could be close to the VDD and VSS rails, respectively. Such clamping allows the current mirror transistors 151-154, and 155-158 to be low voltage devices, enabling higher operating speed and better device matching.